1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices having different properties, and more particularly, to a method for fabricating semiconductor devices of different properties without using masks.
2. Description of the Related Art
In semiconductor integrated circuit design having high integration density and functionality, several semiconductor devices having different functions and properties are often formed on a common substrate. For example, the properties of a semiconductor device such as a metal oxide semiconductor field effective transistor (MOSFET), include, for example, a threshold voltage implant, thickness of a gate oxide layer, and gate conductor work-function of the semiconductor device.
In complementary metal oxide semiconductor (CMOS) technology, since disparity is widened between an internal operating voltage and an external operating voltage, MOSFETs having different properties are needed, such as threshold voltages, different gate oxide thickness, and different gate conductor work-functions. For example, MOSFETs used in speed critical devices are customarily required to have properties such as short channels, low threshold voltages, and thin gate oxide layers. On the other hand, MOSFETs for use of interfacing with external circuitry are required to reliably sustain higher voltages so as to have thicker gate oxide layers and longer channels. Furthermore, in dynamic random access memory (DRAM) circuitry, MOSFETs for use in wordline drivers need to have thick gate oxide layers, while MOSFETs for use in high-performance support circuitry need to have thin gate oxide layers. Thus, DRAM circuitry use MOSFETs having different thickness of gate oxide layers. Yet, use of MOSFETs having different properties are needed for sense amplifier devices in circuitry with low standby current. In such circuitry, MOSFETs used in sense amplifier devices require threshold voltages lower than those required by MOSFETs used in other areas of the circuitry.
In conventional methods for fabricating semiconductor devices having different properties on a common substrate, multiple masks, such as block masks, are required, for example, to protect certain portions of a semiconductor device from subsequent processes. In other words, multiple masks are required to tailor specific properties (electrical characteristics) of each semiconductor device to be used for a particular circuit application. For example, block masks (e.g., costly photo-masks) are required for implantation of unique threshold voltage implant into a semiconductor device so that it may have electrical characteristics, such as off-current, threshold voltage, substrate sensitivity, and pinch-off voltage, for a particular circuit operation. When gate oxide reliability is in issue, selective use of specific thickness of gate oxide layers is often required. Gate conductor work-function of each semiconductor device may also be a consideration for increasing a choice of threshold voltages for semiconductor devices on a common semiconductor substrate.
However, in the conventional methods for fabricating semiconductor devices having different properties, the requirement of multiple masks increases the cost for manufacturing the semiconductor devices having different properties.
Therefore, a need exists for a method for fabricating semiconductor devices on a common semiconductor substrate without using multiple masks, wherein the different semiconductor devices have different properties. Thus, the present invention can advantageously reduce the cost for manufacturing the semiconductor devices having different properties owing to use of such maskless processes.
It is an object of the present invention to provide a method for fabricating semiconductor devices on a common semiconductor substrate, which have different properties, such as different threshold voltages, gate oxide thickness, and gate conductor work-functions.
It is another object of the present invention to provide a method for fabricating semiconductor devices having different properties on a common semiconductor substrate without using multiple masks or masking processes.
To achieve the above and other objects, the present invention provides a method for fabricating semiconductor devices on a semiconductor substrate, wherein properties of the semiconductor devices are different from each other, the method comprising the steps of defining in the semiconductor substrate channel regions which have various lengths, each of the channel regions being formed in a corresponding one of the semiconductor devices; forming an oxide layer on each of the channel regions; and forming a gate conductor material layer on the oxide layer on each of the channel regions, wherein the gate conductor material layer determines a gate conductor work-function of a corresponding semiconductor device. The step of forming an oxide layer preferably includes forming oxide layers on the respective channel regions, the oxide layers having various thickness. The step of forming the gate conductor material layer preferably includes forming gate conductor material layers on the respective oxide layers on the respective channel regions, and the gate conductor material layers have various types of material which determine various types of gate conductor work-functions of the semiconductor devices. A step of implanting the channel regions in sequence may be further included such that the channel regions have doping levels different from each other.
In an aspect of the present invention, there is provided a method for fabricating N semiconductor devices on a semiconductor substrate, wherein properties of the N semiconductor devices are different from each other, the method comprising the steps of (a) forming N openings on the semiconductor substrate, wherein each opening is corresponding to a channel region of each semiconductor device, (b) forming oxide layers of an ith type on surfaces of the N openings, (c) depositing gate conductor material of an ith type over structure of the semiconductor devices, the gate conductor material of the ith type having a gate conductor work-function of an ith type, (d) removing the gate conductor material of the ith type such that a predetermined amount of the gate conductor material of the ith type remains in an ith opening to form a gate conductor material layer of the ith type on top surface in the ith opening and the gate conductor material of the ith type deposited in the structure other than the ith opening is removed, (e) removing the oxide layers of the ith type from openings other than the ith opening, (f) repeating the steps of (a) through (e) from xe2x80x9ci=1xe2x80x9d to xe2x80x9ci=Nxe2x80x9d, and (g) forming at least one layer on surface of each of N gate conductor material layers in the N openings to form a gate conductor, whereby the N semiconductor devices have N gate conductors, respectively, wherein the N gate conductors have N types of gate conductor work-functions.
The method preferably further includes after the step (d) the step of implanting N channel regions of the N semiconductor devices with an ith type implant, whereby augmenting doping levels of channel regions other than first though ith channel regions of first though ith semiconductor devices. An oxide layer in each of the N openings may have a thickness unique to the oxide layer, and the N openings have lengths different from each other. The step (c) preferably includes the step of filling the gate conductor material of the ith type to an extent of completely filling the ith opening. The N openings may have N types of gate conductor material layers, respectively, which are, for example, N types of poly-silicon (or metal) layers. Then, each type of work-function of each semiconductor device is determined by a doping type of a poly-silicon layer of the semiconductor device. The method of the present invention preferably includes in the step of (g) the steps of recessing N gate conductor material layers in the N openings, respectively, and forming the at least one layer on each of the recessed N gate conductor material layers, wherein the at least one layer preferably includes a silicide layer on each of the recessed N gate conductor material layers and an oxide layer on the silicide layer.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.